1. Field of the Invention
The present invention relates to the control of a buffer memory incorporated in a data processing system.
2. Description of the Prior Art
In a data processing system, the time required for accessing a main memory is usually longer than that for arithmetical operation by a processor. To shorten the data processing time, especially the access time, a buffer memory is incorporated in the processor which memory has a shorter access time than the main memory though it has a smaller memory capacity. The buffer memory stores a partial copy of the content of the main memory. In the operation of reading instructions or operands, if the buffer memory stores a copy of data to be read out of the main memory, the copy is read out of the buffer memory so as to diminish the access time.
A table called an address array is provided to indicate which part of the copy of the main memory content is stored in the buffer memory.
The address array is such a table that stores the address of the main memory whose data is stored in the buffer memory correspondingly to the respective blocks of the buffer memory to indicate the correspondence between the main memory and the buffer memory. Each block is the shortest unit of data transferred for copy from the main memory. Accordingly, the content of the address array must be renewed each time the block transfer takes place, so that the address array and the buffer memory operate correspondingly with each other.
Block transfer means the operation in which desired data is transferred from the main memory to the buffer memory to be stored therein.
In a multiprocessing system in which a plurality of data processors, each having a buffer memory, share a single main memory, the following disadvantages may happen. If all or a part of the content of the main memory is rewritten by one data processor, the content of the buffer memory of another data processor which stores the copy of a part of the old content of the main memory necessarily becomes different from the renewed content of the main memory.
Moreover, the same disadvantage takes place when data are additionally written in the main memory by an imput-output processor. Therefore, also in this case, the content of the address array must be accordingly renewed.
According to the conventional multiprocessing system using data processors of congruent type or of set-associative type, whenever data are stored in the main memory, the main memory addresses of the stored data are given to the processors so as to make the contents of the buffer memories of the processors identical, i.e., up to date, with the corresponding parts of the content of the main memory. Namely, at every storing operation (including data transfer from the input-output device to the main memory), the content of the buffer memory of each processor is renewed and the contents of the corresponding columns of the buffer address arrays in the buffer memories of the other processors are checked by the store address. When the store address and the block address registered in a buffer address array are found coincident with each other, the validity bit of the block address is reset or the store address is transferred to other processors to be written in the associated buffer memories.
However, this system mentioned directly above has a drawback in that the arithmetic processing by the processors is stagnant, since this system is an instant response type in which the processing is advanced only after the fact that the other processors which have received the store address have been checked. In the case where at most two processors are used, it is relatively easy to restrict such a drawback to a negligible extent, but if three or four or more processors are used, the drawback proves to be fatal to a high speed basic processor. In order to eliminate such a fatal drawback, there is proposed a method in which the flow of the ordinary processing is kept uniform by the provision of a stack of address registers at the entrance of the store address. However, owing to the provision of the stack, this system requires an increase in hardware and a complicated control for checking the addresses so as not to disturb the flow of the ordinary processing, resulting in further drawbacks in this system.